1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device and a fabricating method thereof.
2. Discussion of the Related Art
Due to their small size, light weight, and low power consumption, flat panel display (FPD) devices have been the subject of much research in the field of information technology. Among the many types of FPD devices, liquid crystal display (LCD) devices, which are used in devices such as notebook personal computers (PCs) and desktop PCs, have excellent color, resolution, and display characteristics. Generally, a liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecules have a definite orientational order in alignment resulting from their thin and long shapes. The alignment direction of the liquid crystal molecules can be controlled by applying an electric field to the liquid crystal molecules. In other words, as the intensity of the electric field is changed, the alignment of the liquid crystal molecules also changes. Since incident light through liquid crystal is refracted based on an orientation of the liquid crystal molecules, due to the optical anisotropy of the aligned liquid crystal molecules, an intensity of the incident light can be controlled and images can be displayed.
Among the various type of LCD devices commonly used, active matrix LCD (AM-LCD) devices where thin film transistors (TFTs) and pixel electrodes connected to the TFTs are disposed in matrix have been developed because of their high resolution and superiority in displaying moving images. In the AM-LCD device, the pixel electrode and a common electrode are formed on first and second substrates, respectively. A vertical electric field generated between the pixel electrode and the common electrode drives a liquid crystal layer between the pixel electrode and the common electrode. The AM-LCD device has properties of high transmittance and high aperture ratio.
FIG. 1 is a schematic cross-sectional view of a related art liquid crystal display device. As shown in FIG. 1, an upper substrate 12 and a lower substrate 14 face and are spaced apart from each other. The upper substrate 12 and the lower substrate 14 are referred to as a color filter substrate and an array substrate, respectively. A liquid crystal layer 16 is interposed between the upper and lower substrates 12 and 14. An active region “A” includes a pixel region “P” and a thin film transistor (TFT) “T” on the lower substrate 14. Further, a data link region “B” adjacent to the active region “A” and a data pad region “C” adjacent to the data link region “B” are defined on the lower substrate 14. The thin film transistor (TFT) “T” includes a gate electrode 18, a semiconductor layer 22, and source and drain electrodes 24 and 26 on an inner surface of the lower substrate 14 in the active region “A.”
A pixel electrode 32 connected to the TFT “T” is formed in the pixel region “P.” A black matrix 34, a color filter layer 35, an overcoat layer 38 and a common electrode 40 are sequentially formed on an inner surface of the upper substrate 12. The black matrix 34 is formed at the data link region “B” and extended over the TFT “T.” The color filter layer 35 including red (R), green (G) and blue (B) colors that are alternately disposed and overlaps the black matrix 34, where one color corresponds to one pixel region. First and second orientation films (not shown) may be formed on the pixel electrode 32 and the common electrode 40, respectively.
A liquid crystal layer 16 is interposed between the first and second orientation films. A spacer 42 is used in the liquid crystal layer 16 to maintain a precise and uniform gap between the upper and lower substrates 12 and 14. A seal pattern 44 is formed between the first and second orientation films of the data link region “B” to maintain a gap for injection of a liquid crystal material and prevent leakage of the injected liquid crystal material. A data pad portion “D” is formed on the lower substrate 14 of the data pad region “C” for connecting the liquid crystal panel to an external circuit. The data pad portion “D” is connected to a data line 25, which is connected to the source electrode 24 of the TFT “T” in FIG. 1, to apply a driving signal to pixels of the liquid crystal panel. First and second polarizing plates 31 and 35 are formed on an outer surface of the upper and lower substrates 12 and 14, respectively. A backlight is disposed under the second polarizing plate 35.
FIG. 2 is a schematic plan view of a related art liquid crystal display device. As shown in FIG. 2, a data line 50 in an active region “A” connects to a data link line 52 in a data link region “B”. A data pad 54 in a data pad region “C” also is connected to the data link region “B”. The data link region “B” is outside of the active region “A” and the data pad region “C” is outside of the data link region “B.” The data pad 54 has a larger width than the data link line 52. A data pad terminal 58 covers the data pad 54 and is connected to the data pad 54 through data pad contact holes 56.
A process of forming a liquid crystal panel from attached upper and lower glass substrates includes a process of cutting the attached substrates into a unit panel. As shown in FIG. 1, the data link region is disposed inside of the data pad region. Glass substrates have a high degree of hardness, and the cutting process is performed by scratching with an ultra hard alloy and breaking the glass substrates with an exterior impact. Since a cutting plane of the upper substrate is disposed over the data link region of the lower substrate, a glass chip generated during the cutting process can scratch the data link line 52 such that the data pad 54 is disconnected from the data line 50.
FIG. 3 is a schematic cross-sectional view taken along a line III—III of FIG. 2. As shown in FIG. 3, a gate insulating layer 20 is formed on a substrate 14 and a data link line 52 is formed on the gate insulating layer 20. A passivation layer 28 is formed on the data link line 52 and the gate insulating layer. The data link line 52 is made of the same material as the data line 50 (of FIG. 2). Generally, the gate insulating layer 20 and the passivation layer 28 are made of silicon nitride (SiNx) or silicon oxide (SiOx).
In a gate pad portion (not shown), a gate link line is made of the same material as a gate line, the gate link line is covered with the gate insulating layer and the passivation layer. Accordingly, the gate link line is not susceptible to the glass chip. However, in the data pad portion, since the data link line has a single layer and only the passivation layer covers the data link line, a break in the data link line due to a glass chip generated during panel cutting can easily occur.